1. Technical Field
The present invention relates generally to computer memory devices and in particular to accessing computer memory devices. Still more particularly, the present invention relates to a method and system for efficiently tracking busy banks within computer memory devices.
2. Description of Related Art
Computer memory typically comprises one or more memory modules (e.g., dual inline memory modules (DIMMs) with one or more memory devices, such as synchronous dynamic random access memory (DRAM) or its static counterpart, SRAM. Standard DIMMs typically will contain 4 to 18 DRAMs and custom designs may contain as many as 72 or more DRAMs.
DRAMs on a DIMM are divided into independently addressable memory blocks, referred to as ranks. Depending on the type of DRAM and DIMM, each rank will span multiple DRAMs ranging from a few to 18 per rank. Typical industry standard DIMMs will contain one or two ranks, with custom DIMMs containing 4, 8, or more ranks. Within each rank on a DIMM there will be some number of independent internal banks of memory that can be accessed in an overlapped manner. The number of banks is DRAM technology dependent but generally the number is 4 or 8 banks.
As the desire for more memory capacity and bandwidth increases, custom DIMMs will be designed with multiple ranks of DRAMs that may have combined totals of 32, 64 or more banks of memory. Further, multiples of such DIMMs are often provided within a single memory system resulting in systems that may have very large numbers of independent banks of memory. For example, a 4 DIMM system with 8 ranks per DIMM and 8 internal banks per DRAM would have a total of 256 banks.
Supporting these large numbers of banks often requires a large amount of logic within the memory controller. Typically a memory controller will contain specific logic (Bank Control Logic—BCL) for each bank in the system to track information and status on the DRAMs within the bank. Included in this logic would be the address range for the memory, the state of the DRAMs (idle, active, etc.), timers to track active states, logic to track open pages, etc. All this logic adds up to a significant amount of silicon area and power consumption in the memory controller. In addition, the cone of logic gets deeper as banks are added and can eventually impact the frequency of operation of the logic or the number of latency cycles to propagate through the logic. For systems that only support small number of banks of memory, this is generally not an issue, but if the system needs to support large number of banks (e.g., greater than 32 banks), then the increased amount of logic to support these banks becomes a significant design challenge.
As is shown in the art, when a bank of the DRAM is accessed, the bank goes into a busy state for a predetermined amount of time before the bank may be accessed again. This predetermined amount of time that the bank will be busy varies based on the DRAM installed and the frequency of operation, but may easily be 16 or more times the length of a data transfer from a bank of memory. With this large busy time, a memory system needs to have multiple banks of memory that can be accessed in an overlapped manner to utilize the available bandwidth on the system data bus. Therefore, adding additional banks of memory and the associated Bank Control Logic to support these additional banks may significantly increase the system memory performance. With each bank added, the additional performance gain becomes less and less, as the system reaches a level where there are more banks of memory available than can be accessed at one time.
A conventional memory controller designed to support a system with a large number of banks of memory, such as 128 or 256 banks, would required adding significant silicon area to contain all the Bank Control Logic blocks needed for each of the supported banks in the memory system. This additional logic will add cost and complexity to the designs, even though the performance gain from adding additional banks past the 32 or 64 banks is not significant. Given that the performance gain for these additional banks of memory is not significant, a method is needed to add the banks of memory without significantly increasing the logic or cost of the memory controller.